As semiconductor processing technologies improve, device geometries of integrated circuits are continually made smaller so that the device density of the entire system can be maximized. This results in MOS transistors within integrated devices having shorter and shorter gate lengths which results in the necessity of a reduction in gate oxide thickness and operating supply voltage in order to support the minimum gate length without excessively high threshold voltages. The minimum allowable gate oxide thickness for a given device is limited by the time dependent dielectric breakdown of the thin oxide at the desired operating voltage. As a result, the operating voltages applied to the gates of MOS transistors within a particular device must be reduced as the gate oxides within these devices are reduced in thickness.
It is often the case that devices of one generation need to communicate with devices of prior generations of integrated systems. For example, a device having a given device geometry and gate oxide thickness may need to have input/output devices constructed on the same semiconductor substrate that have thicker gate oxides to enable the high performance device to communicate at the same voltage levels as surrounding integrated circuits that are operating using prior generations of device geometries and gate voltages. In this manner, a chip having a channel length of 0.25 microns and a corresponding gate voltage of 1.8 volts may also need to have constructed on the same chip transistors having 0.6 micron channels able to operate at 3.3 volts. In this particular example, the high performance devices may have a gate oxide on the order of 40 Angstroms in thickness where the higher voltage input/output devices will have a gate oxide on the order of 80 Angstroms in thickness.
The formation of gate oxide layers having two different thicknesses on the same substrate is very problematic. In order to form these transistors, the gate oxides must be patterned using photolithographic techniques. Using conventional techniques, it is often the case that if two gate oxide thicknesses are needed there will be an occasion for a photoresist mask to be in place proximate to bare semiconductor substrate. This situation can result in the degradation of the surface of the substrate especially in the area intended to be used for high performance transistors.
Accordingly, a need has arisen for a method of forming a semiconductor device having two different gate oxide thicknesses that will not degrade the performance of the high performance transistors within the integrated device.